1. Field of the Invention
The present invention is generally in the field of semiconductor packaging. More specifically, the present invention is in the field of semiconductor packaging using pin grid array packages.
2. Background Art
The semiconductor fabrication industry is continually faced with a demand for dies which must run at increasingly high frequencies. For example, recent RF (xe2x80x9cRadio Frequencyxe2x80x9d) semiconductor devices, which constitute a significant category of semiconductor devices, are required to run at very high frequencies. The requirement of faster devices has resulted in new challenges not only in the fabrication of the die itself, but also in the manufacturing of various packages that are used to provide electrical connection to xe2x80x9coff-chipxe2x80x9d devices. As an example, the demand for higher frequencies means, among other things, that xe2x80x9con-chipxe2x80x9d and xe2x80x9coff-chipxe2x80x9d parasitics must be minimized.
Pin grid array (xe2x80x9cPGAxe2x80x9d) packaging has traditionally been one of the most reliable, low cost, and well known packaging technologies in the integrated circuit (xe2x80x9cICxe2x80x9d) industry and has been used in many microprocessor applications. In PGA technology, the connection between the ceramic substrate and the motherboard is achieved by an array of metal pins. The pins are typically about 2.5 to 3.0 mm in length and might be brazed to a ceramic substrate, e.g. A12O3. In recent years, however, the PGA technology has gone out of favor for high-speed applications, for example in some high frequency RF applications and in Gigabyte/second (Gb/s) data transmission applications, largely due to the relatively high, and difficult to control, impedance of the pins.
As a result of the high, and difficult to control, impedance of PGA pins, PGA technology has been replaced, in high frequency applications, by technologies such as ball grid array (BGA) or column grid array (CGA), both of which also typically use ceramic substrates. BGA technology utilizes an array of solder balls, each approximately 0.5 to 0.6 mm in length, to provide electrical connections. Column grid array (CGA) technology utilizes columns that are similar to, but shorter than, the pins used in PGA technology. The columns used in CGA are approximately 1.75 to 2.0 mm in length and are soldered with two types of solder to prevent physical collapse during the reflow process.
PGA technology, however, offers distinct advantages since the pins in a PGA are able to handle the strain caused by the typically large mismatch in thermal expansion that exists between ceramic substrate materials and organic motherboard materials, for example. A typical ceramic substrate may have a coefficient of thermal expansion (xe2x80x9cCTExe2x80x9d) of about 7 ppm/xc2x0C., while the laminate material of the motherboard may have a CTE of about 50 ppm/xc2x0C., where ppm/xc2x0C. is the parts per million expansion per degree Celsius. Therefore, when the temperature rises, the organic motherboard will expand much faster than the ceramic material, resulting in stress and strains that can potentially cause connection joints to fail. The pins in a PGA package, however, are long enough such that they can handle the strain caused by the CTE mismatch, and can thereby improve the reliability and lifetime of such devices.
Therefore, there exists a need for a novel PGA package which is also suitable for high speed RF or high speed data transmission applications.
The present invention is directed to a pin grid array (xe2x80x9cPGAxe2x80x9d) package with controlled impedance pins. The invention overcomes the need in the art for a novel PGA package which is also suitable for high speed RF or high speed data transmission applications.
According to an embodiment of the invention, a pin grid array package comprises a number of signal pins and ground pins. At least one of the signal pins is a controlled impedance signal pin, i.e. a signal pin whose impedance is adjusted and/or reduced according to the present invention. The pin grid array package also includes a number of ground planes and signal planes.
In one embodiment of the invention, a controlled impedance signal pin is coupled to one of the signal planes by means of a signal via. A number of ground pins surround the controlled impedance signal pin. Each of the ground pins is connected to at least one of the ground planes through respective ground vias. By varying the arrangement, number, and separation distance between the ground pins and the controlled impedance signal pin, the impedance of the signal pin is adjusted and/or reduced.
In one embodiment of the invention, a standard 50 ohm impedance is achieved for the controlled impedance signal pin. In other embodiments of the invention, reference planes, such as power planes, are used instead of ground planes. In that embodiment, a number of reference pins surround the controlled impedance signal pin. Each of the reference pins is connected to at least one of the reference planes through respective reference vias. Depending on the particular circuit or logic function assigned to a signal pin and its adjacent signal pin, a different degree of impedance control and/or reduction can be achieved by the present invention. Various other features and advantages of the present invention are described in the detailed description section below.